The electronic design automation (EDA) tool and intellectual property (IP) core industries have a number of design systems for describing and packaging IP cores for deployment. When these design systems and corresponding core library descriptions are used to assemble designs there is no context or description for the underlying silicon platform upon which the design will be instantiated.
For application specific integrated circuits (ASICs), the disadvantage of the missing context is an uncertainty in the size of the resulting die, number of IO, etc. For structured ASIC platforms, the disadvantage is more pronounced because resources are fixed.
It would be desirable to have a solution for describing platform capabilities in a standard way that can be deployed to third party tools.